<p>NAND  flash memory chips arrange the memory cells in a logical &ldquo;not-and&rdquo;  (NAND) configuration. This arrangement strings together all of the cells  for a common input / output (I/O) bit across all memory pages. <br /> Because  of this arrangement, it is not possible to directly access individual  data bytes within a memory page. The flash memory controller must read  an entire page of memory from the device. Also, an entire page must  usually be programmed at once, although some devices permit partial page  programming. That makes NAND flash unsuitable for most random  byte-access memory applications.The  flash memory controller may additionally divide the 2048 bytes per page  into four sectors of 512 bytes, a typical size for HDDs. But the NAND  flash memory unsuitable for most random byte-access memory applications.<br /> NAND  flash memory is more densely packed on the silicon due to the space  saved by reducing the number of I/O bit lines and ground connections.  NAND flash memory has a lower cost per bit than NOR flash memory. NAND  flash memory is more suitable for data file storage where random  byte-access is not essential. NAND flash memory cells are more  susceptible to disturbances from reading and programming neighboring  pages due to the high density of memory cells on the silicon wafer.<br /> Another  different type of arrangement combines cells into a &ldquo;not-or&rdquo; (NOR)  logic configuration. NOR flash memory allows each memory cell to be  individually addressed and is suitable for random byte-access memory  application.<br /> To  understand how wear leveling is performed on memory within the SSD  flash drive, it is important to understand the architecture layout of  the NAND flash. An SSD is made up of many individual NAND flash chips.  Each individual NAND flash chip is made up of an array of blocks. Within  each block is an array of memory cells called pages (or sectors).Pages  are typically about 512 bytes, but can be as large as 2048 bytes. Each  page incorporates additional overhead bytes to handle such things as ECC  and indexing.</p>