State machine creation and code generation

Hi, there!

I am new to VP-UML and am most interested in state machine modelling and automatic code generation (C++). At first sight getting a state machine diagram done seems to be rather straightforward, but when I activate code generation I see I must have done something wrong. Some questions:

1 - is there a tutorial somewhere?

2 - how can one define a “compound”/super state (i.e containing a state machine itself). Do you necessarily have to employ a “submachine state”?

3 - how do you define the start state of such a state?

4 - I tried using submachines to no avail. The generator complains the state does not exist. How you go around them?

5 - simply adding (call) triggers to transitions seems to have no effect. The only thing that works for me is specifying the “operation” property of transitions. What triggers are for then in VP-UML?

6 - is there anybody out there that has ever had a nice experience using VP-UML to generate state machine code?

Thanks in advance. Cheers,


I’ve finally found some demo animation on state machine creation on the VP-UML site, which sort of clarified the use of triggers. Now what most interests me right is composite state implementation.

I’ve learnt that composite states are created simply by “adding a region” to a state and then dropping other (inner) states there. However, it seems code generation does not support the concept at all, which includes e.g. History states. Am I right or do I miss something?

Thanks in advance. Cheers,

Hello Jorge,

Thanks for your message. For your questions:

  1. you can find the document/sample of the state code feature at

2, 4. currently we do not support generate code with submachine state. You can define nested state to achieve similar effect.

  1. currently we do not support defining how to code looks like in the initial state. We will consider to support this.

  2. we specially design this in order to reduce the work done by user.

If you require any further information, please do not hesitate to contact me again.

Best regards,

Thank you very much for your reply, Rain.

But that’s exactly what’s happening to me: I am trying to use nested states but they are generated as if there’s no nesting. Other things that seem to be just ignored by the code generator: choice and history pseudo-states…

What I might be doing wrong? Just in case any of you would be kind enough to have a look, I’ve attached two problematic VP-UML projects, along with the generated files (.sm, .cpp and .h, where applicable)::

1 -, which generates code, but does not handle nested states correctly. Notice e.g. that state WaitingAppA does not “inherit” behaviour from superstate Active;

2 -, in which I try to use choice states.
In this case, no code is generated, and I get the following error msgs:

C:\Documents and Settings\jorge\My Documents\Dev\SV\code\SVSS4\controller\fsm\turnstile-bidir-singlereader-fsm\ error - no such state as “a”.
C:\Documents and Settings\jorge\My Documents\Dev\SV\code\SVSS4\controller\fsm\turnstile-bidir-singlereader-fsm\ error - no such state as “d”.

Thanks in advance for any pointers. Cheers,

I forgot to mention I am using VP-UML Professional 6.4 (Build 20081023) on winXP.


Hi Jorge,

Thanks for your details and the project files. I’m Lilian Wong, another member in the support team. I’ve forwarded the issue to our engineers to investigate. Once there is any feedback, I’ll come back to you immediately. If there is anything I can help, please feel free to contact me.

Best regards,
Lilian Wong

Hi Jorge,

I regret to let you know that we do not handle nested state in state code generation (we treat as non-nested state), also we do not support state code generation for choice (or exit, or history). At the moment we only support simple state machine diagram in state code generation, I’m sorry about this fact.

If there is anything we can do to help, please do not hesitate to ask.

Best regards,
Lilian Wong

Hi Lilian and all other VP team members,

are there plans to support more complete code generation for state diagrams in the future? I think the existing possibilities are not really sufficient :frowning: At most, I am missing the possibility to handle hierarchical state diagrams.

What I am also missing is documentation on how to build complex state diagrams. For example, Submachine State handling is not mentioned in the User’s Guide at all.

Kind regards from Germany


Hi Stephen,

Thanks for your post. I’ve fired a feature request to our engineers to study the feasibility to support complex state diagram in state code generation. If there is any news on this issue, I’ll come back to you all immediately.

About build complex state diagram, we fully follow UML Specification ( ) and the modeling is straight forward. If you found any technical difficulty on state diagram modeling, please feel free to contact me.

Best regards,
Lilian Wong

Hi user,

I would like to let you know that we will support advance state machine code generation in the the future (plan to be available in second half of 2009).

If there is any further news on this issue, I’ll come back to you immediately.

Best regards,
Lilian Wong

Dear VP-Team,

how far did you come with the above mentioned terms up to now?
I’m just testing the trial versions of VP-UML and SDE with C++. Seems to me that code generation of orthogonal, parallel or concurent states (how you would like to call them) is still not possible. Or am I wrong?
I created a composite state with two regions inside, each containing a simple (sub) state machine and a single state with a transitiion to the first one. Generating the state machine’s source with “State Machine Code -> Generate Code”, I found out, that with the transiton from the single to the composite state only one of its containing regions gets active.

Perhaps, I did somtehing wrong. Can you help me?